1. Field of the Invention
This invention relates to a power semiconductor device and a fabrication method thereof, and more particularly relates to a trenched power semiconductor device and a fabrication method thereof.
2. Description of the Prior Art
A typical planar power semiconductor device has the gate electrode placed over the substrate for generating a conductive current flowing along the surface of the substrate. The reduction of cell pitch is thus constrained by the formation of the planar gate electrode. In contrast with the planar device, the trenched one has the gate electrode placed in a vertical trench for generating a vertical conductive current in replace of the horizontal conductive current. Therefore, the distance between neighboring cells can be reduced and layout integration can be improved.
FIG. 1 is a cross-section view of a typical trenched metal oxide semiconductor field effect transistor (MOSFET). As shown, the trenched MOSFET has an N-type heavily doped substrate 10, an N-type lightly doped epitaxial layer 12, a plurality of gate trenches 14, a plurality of gate structures 16, a plurality of P-type bodies 17, a plurality of source regions 18, and an interlayer dielectric layer 19. The N-type lightly doped epitaxial layer 12 is located on the N-type heavily doped substrate 10. The gate trenches 14 are located in the N-type lightly doped epitaxial layer 12. The gate structures 16 are located in the respective gate trenches 14. The P-type bodies 17 are located in an upper portion of the N-type lightly doped epitaxial layer 12, and the gate trenches 14 are encircled by the P-type bodies 17. The gate structures 16 are covered with a gate dielectric layer 15 so as to electrically isolate the gate structures 16 from the P-type bodies 17 and the N-type lightly doped epitaxial layer 12. The source regions 18 are located in a surface layer of the P-type bodies 17, and the gate trenches 14 are encircled by the source regions 18. The interlayer dielectric layer 19 is deposited over the gate structures 16 and has a plurality of source contact windows formed therein to expose the source regions 18.
In general, source voltage of the trenched MOSFET is applied to the source regions 18 through a source metal pad (not shown in this figure) located above the interlayer dielectric layer 19, the gate voltage is applied to the gate structures 16 through a gate metal pad (not shown in this figure) located above the interlayer dielectric layer 19, and the drain voltage is applied to the N-type heavily doped substrate 10 through a drain metal pad (not shown in this figure) located on a lower surface of the N-type heavily doped substrate 10. The bonding steps for connecting the metal pads on the both sides of the substrate 10 to the lead frame may results in an unwanted limitation to the packaging process.
Accordingly, how to overcome the above mentioned drawbacks without complicating the structure and the fabrication method of the trenched power semiconductor devices, is an important issue in this technology field.